Conteúdo Sugerido para
Disciplina de tópicos em Arquiteturas:
Arquiteturas Avançadas
- Revisão MIPS: Pipeline
- Revisão MIPS: Dependências Dados e Controle
- Fetch stage: (block size, fetch buffer, trace cache)
- Decode stage: (uops, decode buffer, decoded cache)
- Branch prediction Pt.1: (Predication, Address
- Prediction – Branch Target Buffer, Call/Return Stack)
- Branch prediction Pt.2: (Direction Prediction: Static, 1 Bit, 2 Bit, Two Level, Global/Local Signtures)
- Precise exceptions and interruptions: (Reorder buffer, History buffer, Future register file, Checkpointing)
- Rename, Dispatch, Execute, Commit stages: (Scoreboard, Tomasulo, Centralized/Distributed Reservation stations)
- Caches Pt.1 – Associativity, Line Size, Hierarchy
- Caches Pt.2 – Replacement policy, Parallel/Sequential Lookup
- Caches Pt.3 – Multi-ports, Multi-banked, Non-blocking caches
- Prefetching 1 – Software
- Prefetching 2 – Hardware
- Multithreading + Multi-Core
- Networks-on-Chip (NoC) (Topologies + Routing)
- Memory Management Unit (MMU) (Translation Lookaside Buffer)
- Memory Management Unit (MMU) (Paging and Caches)
- Memory Controller + Double Data Rate Memories (DDR)
- Hybrid Memory Cubes (HMC) and High Bandwidth Memories (HBM)