{"id":642,"date":"2021-03-31T10:41:38","date_gmt":"2021-03-31T13:41:38","guid":{"rendered":"http:\/\/web.inf.ufpr.br\/mazalves\/?page_id=642"},"modified":"2021-03-31T10:43:07","modified_gmt":"2021-03-31T13:43:07","slug":"dis-proj-digitais-e-microprocessadores","status":"publish","type":"page","link":"https:\/\/web.inf.ufpr.br\/mazalves\/dis-proj-digitais-e-microprocessadores\/","title":{"rendered":"Disciplina de Proj. Digitais e Microprocessadores"},"content":{"rendered":"\t\t<div data-elementor-type=\"wp-page\" data-elementor-id=\"642\" class=\"elementor elementor-642\">\n\t\t\t\t\t\t<section class=\"elementor-section elementor-top-section elementor-element elementor-element-4b8247d3 elementor-section-boxed elementor-section-height-default elementor-section-height-default\" data-id=\"4b8247d3\" data-element_type=\"section\" data-e-type=\"section\">\n\t\t\t\t\t\t<div class=\"elementor-container elementor-column-gap-default\">\n\t\t\t\t\t<div class=\"elementor-column elementor-col-100 elementor-top-column elementor-element elementor-element-434bed22\" data-id=\"434bed22\" data-element_type=\"column\" data-e-type=\"column\">\n\t\t\t<div class=\"elementor-widget-wrap elementor-element-populated\">\n\t\t\t\t\t\t<div class=\"elementor-element elementor-element-3b2899f elementor-widget elementor-widget-heading\" data-id=\"3b2899f\" data-element_type=\"widget\" data-e-type=\"widget\" data-widget_type=\"heading.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t<h2 class=\"elementor-heading-title elementor-size-default\">Conte\u00fado Sugerido para <br>Disciplina de Arquitetura de Computadores<\/h2>\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<div class=\"elementor-element elementor-element-52281cc3 elementor-widget elementor-widget-text-editor\" data-id=\"52281cc3\" data-element_type=\"widget\" data-e-type=\"widget\" data-widget_type=\"text-editor.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t\t\t\t\t<ul><li><p>Apresenta\u00e7\u00e3o e revis\u00e3o de l\u00f3gica e simplifica\u00e7\u00f5es<\/p><\/li><li><p>Revis\u00e3o de circuitos combinacionais<\/p><\/li><li><p>Implementa\u00e7\u00e3o em CMOS, transistores e portas l\u00f3gicas<\/p><\/li><li><p>Implementa\u00e7\u00e3o em CMOS, circuitos combinacionais<\/p><\/li><li><p>Atrasos, tempo de propaga\u00e7\u00e3o e contamina\u00e7\u00e3o<\/p><\/li><li><p>Circuitos de mem\u00f3rias RAM<\/p><\/li><li><p>Lab.: Modelagem estrutural em VHDL<\/p><\/li><li><p>Lab.: Modelagem de circuitos combinacionais<\/p><\/li><li><p>ULA, somador e subtrator com e sem propaga\u00e7\u00e3o<\/p><\/li><li><p>Lab.: Modelagem de somadores r\u00e1pidos<\/p><\/li><li><p>Multiplicador combinacional<\/p><\/li><li><p>Circuitos sequ\u00eanciais, Latches e Flip-Flops com atrasos<\/p><\/li><li><p>Registradores e contadores<\/p><\/li><li><p>Lab.: Modelagem de circuitos sequ\u00eanciais.<\/p><\/li><li><p>M\u00e1quinas de estados finitos Moore e Mealy<\/p><\/li><li><p>Lab.: Modelagem de contadores simples<\/p><\/li><li><p>Setup e hold time (clock skew setup)<\/p><\/li><li><p>Exemplos de circuitos complexos<\/p><\/li><li><p>MIPS: Conjunto de instru\u00e7\u00f5es<\/p><\/li><li><p>MIPS: Instru\u00e7\u00f5es ULA e Mem\u00f3ria<\/p><\/li><li><p>MIPS: Instru\u00e7\u00f5es de controle de fluxo, itera\u00e7\u00e3o<\/p><\/li><li><p>MIPS: Suporte a fun\u00e7\u00f5es, registros de ativa\u00e7\u00e3o, recurs\u00e3o<\/p><\/li><li><p>MIPS: Tipos de instru\u00e7\u00f5es (R, I, J) e opera\u00e7\u00f5es ADD,ORI,LW,SW,BEQ,J<\/p><\/li><li><p>MIPS: Circuito de dados, Temporiza\u00e7\u00e3o e atrasos<\/p><\/li><li><p>Sistemas de mem\u00f3ria e protocolo de comunica\u00e7\u00e3o<\/p><\/li><\/ul>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/section>\n\t\t\t\t<\/div>\n\t\t","protected":false},"excerpt":{"rendered":"<p>Conte\u00fado Sugerido para Disciplina de Arquitetura de Computadores Apresenta\u00e7\u00e3o e revis\u00e3o de l\u00f3gica e simplifica\u00e7\u00f5es Revis\u00e3o de circuitos combinacionais Implementa\u00e7\u00e3o em CMOS, transistores e portas l\u00f3gicas Implementa\u00e7\u00e3o em CMOS, circuitos combinacionais Atrasos, tempo de propaga\u00e7\u00e3o e contamina\u00e7\u00e3o Circuitos de mem\u00f3rias RAM Lab.: Modelagem estrutural em VHDL Lab.: Modelagem de circuitos combinacionais ULA, somador e subtrator&hellip;<\/p>\n","protected":false},"author":13,"featured_media":0,"parent":0,"menu_order":0,"comment_status":"closed","ping_status":"closed","template":"","meta":{"footnotes":""},"class_list":["post-642","page","type-page","status-publish","hentry"],"_links":{"self":[{"href":"https:\/\/web.inf.ufpr.br\/mazalves\/wp-json\/wp\/v2\/pages\/642","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/web.inf.ufpr.br\/mazalves\/wp-json\/wp\/v2\/pages"}],"about":[{"href":"https:\/\/web.inf.ufpr.br\/mazalves\/wp-json\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"https:\/\/web.inf.ufpr.br\/mazalves\/wp-json\/wp\/v2\/users\/13"}],"replies":[{"embeddable":true,"href":"https:\/\/web.inf.ufpr.br\/mazalves\/wp-json\/wp\/v2\/comments?post=642"}],"version-history":[{"count":4,"href":"https:\/\/web.inf.ufpr.br\/mazalves\/wp-json\/wp\/v2\/pages\/642\/revisions"}],"predecessor-version":[{"id":646,"href":"https:\/\/web.inf.ufpr.br\/mazalves\/wp-json\/wp\/v2\/pages\/642\/revisions\/646"}],"wp:attachment":[{"href":"https:\/\/web.inf.ufpr.br\/mazalves\/wp-json\/wp\/v2\/media?parent=642"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}