{"id":615,"date":"2021-03-31T10:24:10","date_gmt":"2021-03-31T13:24:10","guid":{"rendered":"http:\/\/web.inf.ufpr.br\/mazalves\/?page_id=615"},"modified":"2021-03-31T10:36:39","modified_gmt":"2021-03-31T13:36:39","slug":"dis-topicos-em-arquiteturas","status":"publish","type":"page","link":"https:\/\/web.inf.ufpr.br\/mazalves\/dis-topicos-em-arquiteturas\/","title":{"rendered":"Disciplina de T\u00f3picos em Arquiteturas"},"content":{"rendered":"\t\t
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Conte\u00fado Sugerido para
Disciplina de t\u00f3picos em Arquiteturas:
Arquiteturas Avan\u00e7adas<\/h2>\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t
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  • Revis\u00e3o MIPS: Pipeline <\/li>
  • Revis\u00e3o MIPS: Depend\u00eancias Dados e Controle <\/li>
  • Fetch stage: (block size, fetch buffer, trace cache)<\/li>
  • Decode stage: (uops, decode buffer, decoded cache)<\/li>
  • Branch prediction Pt.1: (Predication, Address<\/li>
  • Prediction – Branch Target Buffer, Call\/Return Stack)<\/li>
  • Branch prediction Pt.2: (Direction Prediction: Static, 1 Bit, 2 Bit, Two Level, Global\/Local Signtures)<\/li>
  • Precise exceptions and interruptions: (Reorder buffer, History buffer, Future register file, Checkpointing)<\/li>
  • Rename, Dispatch, Execute, Commit stages: (Scoreboard, Tomasulo, Centralized\/Distributed Reservation stations)<\/li>
  • Caches Pt.1 \u2013 Associativity, Line Size, Hierarchy<\/li>
  • Caches Pt.2 \u2013 Replacement policy, Parallel\/Sequential Lookup<\/li>
  • Caches Pt.3 \u2013 Multi-ports, Multi-banked, Non-blocking caches<\/li>
  • Prefetching 1 \u2013 Software<\/li>
  • Prefetching 2 \u2013 Hardware<\/li>
  • Multithreading + Multi-Core<\/li>
  • Networks-on-Chip (NoC) (Topologies + Routing)<\/li>
  • Memory Management Unit (MMU) (Translation Lookaside Buffer)<\/li>
  • Memory Management Unit (MMU) (Paging and Caches)<\/li>
  • Memory Controller + Double Data Rate Memories (DDR)<\/li>
  • Hybrid Memory Cubes (HMC) and High Bandwidth Memories (HBM)<\/li><\/ul>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/section>\n\t\t\t\t<\/div>\n\t\t","protected":false},"excerpt":{"rendered":"

    Conte\u00fado Sugerido para Disciplina de t\u00f3picos em Arquiteturas:Arquiteturas Avan\u00e7adas Revis\u00e3o MIPS: Pipeline Revis\u00e3o MIPS: Depend\u00eancias Dados e Controle Fetch stage: (block size, fetch buffer, trace cache) Decode stage: (uops, decode buffer, decoded cache) Branch prediction Pt.1: (Predication, Address Prediction – Branch Target Buffer, Call\/Return Stack) Branch prediction Pt.2: (Direction Prediction: Static, 1 Bit, 2 Bit,…<\/p>\n","protected":false},"author":13,"featured_media":0,"parent":0,"menu_order":0,"comment_status":"closed","ping_status":"closed","template":"","meta":{"footnotes":""},"class_list":["post-615","page","type-page","status-publish","hentry"],"_links":{"self":[{"href":"https:\/\/web.inf.ufpr.br\/mazalves\/wp-json\/wp\/v2\/pages\/615","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/web.inf.ufpr.br\/mazalves\/wp-json\/wp\/v2\/pages"}],"about":[{"href":"https:\/\/web.inf.ufpr.br\/mazalves\/wp-json\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"https:\/\/web.inf.ufpr.br\/mazalves\/wp-json\/wp\/v2\/users\/13"}],"replies":[{"embeddable":true,"href":"https:\/\/web.inf.ufpr.br\/mazalves\/wp-json\/wp\/v2\/comments?post=615"}],"version-history":[{"count":3,"href":"https:\/\/web.inf.ufpr.br\/mazalves\/wp-json\/wp\/v2\/pages\/615\/revisions"}],"predecessor-version":[{"id":618,"href":"https:\/\/web.inf.ufpr.br\/mazalves\/wp-json\/wp\/v2\/pages\/615\/revisions\/618"}],"wp:attachment":[{"href":"https:\/\/web.inf.ufpr.br\/mazalves\/wp-json\/wp\/v2\/media?parent=615"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}