{"id":592,"date":"2021-03-31T09:35:42","date_gmt":"2021-03-31T12:35:42","guid":{"rendered":"http:\/\/web.inf.ufpr.br\/mazalves\/?page_id=592"},"modified":"2021-04-29T15:26:47","modified_gmt":"2021-04-29T18:26:47","slug":"dis-arquitetura-de-computadores","status":"publish","type":"page","link":"https:\/\/web.inf.ufpr.br\/mazalves\/dis-arquitetura-de-computadores\/","title":{"rendered":"Disciplina de Arquitetura de Computadores"},"content":{"rendered":"\t\t<div data-elementor-type=\"wp-page\" data-elementor-id=\"592\" class=\"elementor elementor-592\">\n\t\t\t\t\t\t<section class=\"elementor-section elementor-top-section elementor-element elementor-element-abf6d8e elementor-section-boxed elementor-section-height-default elementor-section-height-default\" data-id=\"abf6d8e\" data-element_type=\"section\" data-e-type=\"section\">\n\t\t\t\t\t\t<div class=\"elementor-container elementor-column-gap-default\">\n\t\t\t\t\t<div class=\"elementor-column elementor-col-100 elementor-top-column elementor-element elementor-element-a6b9b2c\" data-id=\"a6b9b2c\" data-element_type=\"column\" data-e-type=\"column\">\n\t\t\t<div class=\"elementor-widget-wrap elementor-element-populated\">\n\t\t\t\t\t\t<div class=\"elementor-element elementor-element-f3f029b elementor-widget elementor-widget-heading\" data-id=\"f3f029b\" data-element_type=\"widget\" data-e-type=\"widget\" data-widget_type=\"heading.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t<h2 class=\"elementor-heading-title elementor-size-default\">Conte\u00fado Sugerido para <br>Disciplina de Arquitetura de Computadores<\/h2>\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<div class=\"elementor-element elementor-element-8af0f10 elementor-widget elementor-widget-text-editor\" data-id=\"8af0f10\" data-element_type=\"widget\" data-e-type=\"widget\" data-widget_type=\"text-editor.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t\t\t\t\t<ul><li>Apresenta\u00e7\u00e3o da disciplina<\/li><li>MIPS mono-ciclo &#8211; Bloco Operacional<\/li><li>MIPS mono-ciclo &#8211; Bloco de Controle<\/li><li>Caracter\u00edsticas da ISA e Processadores RISC<\/li><li>MIPS multi-ciclo &#8211; Bloco operacional<\/li><li>MIPS multi-ciclo &#8211; Bloco de controle (Vis\u00e3o Geral FSM e Sinais de Controle)<\/li><li>MIPS multi-ciclo &#8211; Bloco de controle (FSM e Microprograma\u00e7\u00e3o)<\/li><li>An\u00e1lise de desempenho<\/li><li>MIPS pipeline &#8211; Bloco operacional e de controle<\/li><li>MIPS pipeline &#8211; Depend\u00eancias de dados<\/li><li>MIPS pipeline &#8211; Depend\u00eancias de controle<\/li><li>Aritm\u00e9tica Bin\u00e1ria \u2013 Inteiros e Ponto Flutuante<\/li><li>Pipelines especializados e Exce\u00e7\u00f5es precisas<\/li><li>Processadores superescalares e Execu\u00e7\u00e3o fora de ordem<\/li><li>Processadores VLIW<\/li><li>Taxonomia de Flynn<\/li><li>Processadores Multithreading<\/li><li>Mem\u00f3ria cache Pt.1<\/li><li>Mem\u00f3ria cache Pt.2\u00a0<\/li><li>Interconex\u00f5es<\/li><li>Mem\u00f3ria virtual Pt.1<\/li><li>Mem\u00f3ria virtual Pt.2<\/li><li>Mem\u00f3rias DDR \/ Mem\u00f3rias Inteligentes \/ 3D stack<\/li><\/ul>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<div class=\"elementor-element elementor-element-6c2fafa elementor-widget elementor-widget-video\" data-id=\"6c2fafa\" data-element_type=\"widget\" data-e-type=\"widget\" data-settings=\"{&quot;youtube_url&quot;:&quot;https:\\\/\\\/www.youtube.com\\\/watch?v=bqthDPoNf3A&amp;list=PL_9px37PNj6q8Ac7y6rbXJFfloBAh7JcT&quot;,&quot;autoplay&quot;:&quot;yes&quot;,&quot;mute&quot;:&quot;yes&quot;,&quot;video_type&quot;:&quot;youtube&quot;,&quot;controls&quot;:&quot;yes&quot;}\" data-widget_type=\"video.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t\t\t<div class=\"elementor-wrapper elementor-open-inline\">\n\t\t\t<div class=\"elementor-video\"><\/div>\t\t<\/div>\n\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/section>\n\t\t\t\t<\/div>\n\t\t","protected":false},"excerpt":{"rendered":"<p>Conte\u00fado Sugerido para Disciplina de Arquitetura de Computadores Apresenta\u00e7\u00e3o da disciplina MIPS mono-ciclo &#8211; Bloco Operacional MIPS mono-ciclo &#8211; Bloco de Controle Caracter\u00edsticas da ISA e Processadores RISC MIPS multi-ciclo &#8211; Bloco operacional MIPS multi-ciclo &#8211; Bloco de controle (Vis\u00e3o Geral FSM e Sinais de Controle) MIPS multi-ciclo &#8211; Bloco de controle (FSM e Microprograma\u00e7\u00e3o)&hellip;<\/p>\n","protected":false},"author":13,"featured_media":0,"parent":0,"menu_order":0,"comment_status":"closed","ping_status":"closed","template":"","meta":{"footnotes":""},"class_list":["post-592","page","type-page","status-publish","hentry"],"_links":{"self":[{"href":"https:\/\/web.inf.ufpr.br\/mazalves\/wp-json\/wp\/v2\/pages\/592","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/web.inf.ufpr.br\/mazalves\/wp-json\/wp\/v2\/pages"}],"about":[{"href":"https:\/\/web.inf.ufpr.br\/mazalves\/wp-json\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"https:\/\/web.inf.ufpr.br\/mazalves\/wp-json\/wp\/v2\/users\/13"}],"replies":[{"embeddable":true,"href":"https:\/\/web.inf.ufpr.br\/mazalves\/wp-json\/wp\/v2\/comments?post=592"}],"version-history":[{"count":12,"href":"https:\/\/web.inf.ufpr.br\/mazalves\/wp-json\/wp\/v2\/pages\/592\/revisions"}],"predecessor-version":[{"id":790,"href":"https:\/\/web.inf.ufpr.br\/mazalves\/wp-json\/wp\/v2\/pages\/592\/revisions\/790"}],"wp:attachment":[{"href":"https:\/\/web.inf.ufpr.br\/mazalves\/wp-json\/wp\/v2\/media?parent=592"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}